Advanced model order reduction techniques in VLSI design

Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the way to higher operating speeds and smaller feature sizes. This book presents a systematic introduction to, and treatment of, the key MOR methods employed in general linear circuits, using real-world examples to illustrate the advantages and disadvantages of each algorithm. Following a review of traditional projection-based techniques, coverage progresses to more advanced MOR methods for VLSI design, including HMOR, passive truncated balanced realization (TBR) methods, efficient inductance modeling via the VPEC model, and structure-preserving MOR techniques. Where possible, numerical methods are approached from the CAD engineer's perspective, avoiding complex mathematics and allowing the reader to take on real design problems and develop more effective tools. With practical examples and over 100 illustrations, this book is suitable for researchers and graduate students of electrical and computer engineering, as well as practitioners working in the VLSI design industry.

• Contents p. v
• Figures p. viii
• Tables p. xiv
• Foreword p. xv
• Acknowledgments p. xvii
• 1 Introduction p. 1
• 1.1 The need for compact modeling of interconnects p. 1
• 1.2 Interconnect analysis and modeling methods in a nutshell p. 2
• 1.3 Book outline p. 4
• 1.4 Summary p. 7
• 2 Projection-based model order reduction algorithms p. 8
• 2.1 Moments and moment-matching methods p. 8
• 2.2 Moment computation in MNA formulation p. 11
• 2.3 Asymptotic waveform evaluation p. 13
• 2.4 Projection-based model order reduction methods p. 20
• 2.5 Numerical examples p. 32
• 2.6 Historical notes p. 32
• 2.7 Summary p. 34
• 2.8 Appendices p. 34
• 3 Truncated balanced realization methods for MOR p. 37
• 3.1 Introduction p. 37
• 3.2 The singular value decomposition (SVD) p. 38
• 3.3 Proper orthogonal decomposition (POD) p. 38
• 3.4 Classic truncated balanced realization methods p. 39
• 3.5 Passive-preserving truncated balanced realization methods p. 43
• 3.6 Hybrid TBR and combined TBR-Xrylov subspace methods p. 45
• 3.7 Empirical TBR and poor man's TBR p. 45
• 3.8 Computational complexities of TBR methods p. 47
• 3.9 Practical implementation and numerical issues p. 48
• 3.10 Numerical examples p. 53
• 3.11 Summary p. 54
• 4 Passive balanced truncation of linear systems in descriptor form p. 56
• 4.1 Introduction p. 56
• 4.2 The passive balanced truncation algorithm: PriTBR p. 57
• 4.3 Structure-preserved balanced truncation p. 60
• 4.4 Numerical examples p. 62
• 4.5 Summary p. 64
• 5 Passive hierarchical model order reduction p. 67
• 5.1 Overview of hierarchical MOR algorithm p. 68
• 5.2 DDD-based hierarchical decomposition p. 70
• 5.3 Hierarchical reduction versus moment-matching p. 76
• 5.4 Preservation of reciprocity p. 80
• 5.5 Multi-point expansion hierarchical reduction p. 81
• 5.6 Numerical examples p. 84
• 5.7 Summary p. 91
• 5.8 Historical notes on node-elimination-based reduction methods p. 91
• 6 Terminal reduction of linear dynamic circuits p. 93
• 6.1 Review of the SVDMOR method p. 95
• 6.2 Input and output moment matrices p. 96
• 6.3 The extended-SVDMOR (ESVDMOR) method p. 99
• 6.4 Determination of cluster number by SVD p. 102
• 6.5 K-means clustering algorithm p. 104
• 6.6 TermMerg algorithm p. 106
• 6.7 Numerical examples p. 111
• 6.8 Summary p. 116
• 7 Vector-potential equivalent circuit for inductance modeling p. 118
• 7.1 Vector-potential equivalent circuit p. 119
• 7.2 VPEC via PEEC inversion p. 124
• 7.3 Numerical examples p. 128
• 7.4 Inductance models in hierarchical reduction p. 131
• 7.5 Summary p. 136
• 8 Structure-preserving model order reduction p. 137
• 8.1 Introduction p. 137
• 8.2 Chapter overview p. 138
• 8.3 Background p. 139
• 8.4 Block-structure-preserving model reduction p. 141
• 8.5 TBS method p. 144
• 8.6 Two-level analysis p. 149
• 8.7 Numerical examples p. 151
• 8.8 Summary p. 157
• 9 Block structure-preserving reduction for RLCK circuits p. 158
• 9.1 Introduction p. 158
• 9.2 Block structure-preserving model reduction p. 159
• 9.3 Structure preservation for admittance transfer-function matrices p. 161
• 9.4 General block structure-preserving MOR method p. 163
• 9.5 Numerical examples p. 167
• 9.6 Summary p. 169
• 9.7 Appendix p. 170
• 10 Model optimization and passivity enforcement p. 172
• 10.1 Passivity enforcement p. 172
• 10.2 Model optimisation for active circuits p. 176
• 10.3 Optimization for magnitude and phase responses p. 178
• 10.4 Numerical examples p. 181
• 10.5 Summary p. 185
• 11 General multi-port circuit realization p. 187
• 11.1 Review of existing circuit-realization methods p. 187
• 11.2 General multi-port network realization p. 195
• 11.3 Multi-port non-reciprocal circuit realization p. 197
• 11.4 Numerical examples p. 199
• 11.5 Summary p. 203
• 12 Reduction for multi-terminal interconnect circuits p. 204
• 12.1 Introduction p. 204
• 12.2 Problems of subspace projection-based MOR methods p. 205
• 12.3 Model order reduction for multiple-terminal circuits: MTermMOR p. 208
• 12.4 Numerical examples p. 212
• 12.5 Summary p. 214
• 13 Passive modeling by signal waveform shaping p. 215
• 13.1 Introduction p. 215
• 13.2 Passivity and positive-realness p. 217
• 13.3 Conditional passivity and positive-realness p. 218
• 13.4 Passivity enforcement by waveform shaping p. 221
• 13.5 Numerical examples p. 225
• 13.6 Summary p. 226
• References p. 229
• Index p. 238